The apparatus of claim 1, further comprising detection circuitry to: detect one or more attributes of the PHY circuitry and determine that the recalibration should be performed based on the one or more attributes.ĥ. The apparatus of claim 1, wherein the value of the particular bit is to be reset automatically after a number of clock cycles.Ĥ. The apparatus of claim 1, wherein the write command comprises a committed write.ģ. An apparatus comprising: physical layer (PHY) circuitry a memory to implement a message bus register, wherein a set of control and status signals are mapped to bits of the message bus register, and the set of control and status signals comprises a recalibration request signal mapped to a particular one of the bits of the message bus register and an interface to couple to a controller, wherein the interface comprises a PHY Interface for the PCI Express (PIPE)-based interface, and the interface comprises: a set of data pins comprising transmit data pins to send data to the controller and receive data pins to receive data from the controller a particular set of pins to implement a message bus interface, wherein a write command is to be received from the controller over the message bus interface to write a value to the particular bit and recalibration circuitry to perform a recalibration of the PHY circuitry based on the value written to the particular bit.Ģ.
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